1. Technical Field
The present invention relates generally to an improved data processing system and in particular, to an improved method and apparatus for transferring data across a bus in a data processing system. Still more particularly, the present invention relates to a method and apparatus for transferring data across a bus using intelligent bus arbitration.
2. Description of the Related Art
In computer systems, a bus is a means by which electrical signals are communicated back and forth between a central processor, memory, and other devices, such as input and output adapters. In a single processor data processing system, the bus may be a simple plurality of electrical conductors linking the various components of the system. In multiple processor and other more sophisticated computer systems, however, the bus may become more complex and play an active role in directing the various signals between the components of the computer system. In particular, multi-processor data processing systems are characterized by a plurality of processors, which function as master devices and share a common bus.
Additionally, these systems include a plurality of input/output devices, which function as slaves, and also share the common bus so that masters and slaves may communicate with one another. In such a system, only one master device and one slave device may communicate with each other at any given point in time. In this type of system, the bus architecture allows more than one device to control or gain ownership of the bus. A mechanism must exist to decide which device is permitted ownership of the bus at any particular time. Most often, a scheme known as "arbitration" is employed to determine which device will be the next bus owner. The decision as to who will be the next bus owner is made using various arbitration methods, such as, for example, assigning a priority to each of the competing master devices. Irrespective of the particular arbitration method employed, a problem arises when a slave device selected by the master device to perform a data transfer is either busy or slow to respond. Typically, one of a number of priority-based schemes are employed for determining what device should next be granted the bus. The presently available methods are effective at dividing up bus bandwidth, but do nothing to improve the bandwidth.
Some devices frequently enter a state of long duration in which they generate a bus retry in response to any attempted transaction. Since the master device initiating the retry transfer continues attempting to successfully complete that transfer, the bus experiences retries for a large number of consecutive accesses. This behavior consumes valuable bus bandwidth in an extremely inefficient manner. Additionally, most modern buses are oriented towards large burst transfers because arbitration bus-on and bus-off protocols consume relatively large amounts of time. A retry, in which no data is actually transferred, but at the full arbitration bus-on and bus-off costs, is a wasteful transaction. In lightly loaded or single initiator systems containing few or only a single master device, this is of little or no consequence because the bus is not being or cannot be used by other devices. In heavily loaded systems containing multiple master devices, this type of arbitration reduces the amount of bandwidth available to other devices. Therefore, it would be advantageous to have a method and apparatus for increasing the bandwidth available to other devices in data processing systems containing devices that enter a long state of unavailability.